B-174327, MAY 12, 1972

B-174327, MAY 12, 1972

BID PROTEST - NONRESPONSIVENESS - TECHNICAL ACCEPTABILITY DECISION DENYING THE PROTEST OF DIGITAL DEVICES, INC., AGAINST REJECTION OF ITS PROPOSAL AS NONRESPONSIVE TO AN RFP ISSUED BY GODDARD SPACE FLIGHT CENTER, NASA, FOR EIGHT TRIPLE REDUNDANT BINARY CODED DECIMAL TO BINARY CONVERTERS, SPARE PARTS, AND DOCUMENTATION. THERE IS NO SUPPORT FOR PROTESTANT'S ALLEGATION THAT THE TERM "FULL ADDER" IS BROAD ENOUGH TO INCLUDE BOTH ADDITION AND SUBTRACTION. IT IS THE OPINION OF THE COMP. GEN. THAT THE EVALUATION WAS IN ACCORDANCE WITH THE SPECIFICATIONS AND SINCE DIGITAL FAILED TO CHANGE THE CONFIGURATION OF THE SECOND STAGE OF ITS CONVERTER, THERE EXISTS NO BASIS FOR DISAGREEING WITH THE CONTRACTING OFFICER'S DETERMINATION THAT ITS PROPOSAL WAS TECHNICALLY UNACCEPTABLE. ACCORDINGLY, THE PROTEST MUST BE DENIED.

TO DIGITAL DEVICES, INC.:

WE REFER TO YOUR PROTEST AGAINST A DETERMINATION THAT YOUR PROPOSAL WAS TECHNICALLY UNACCEPTABLE, AND THEREFORE NOT RESPONSIVE, TO THE REQUIREMENTS SET FORTH IN REQUEST FOR PROPOSALS 26517-333, ISSUED BY GODDARD SPACE FLIGHT CENTER, NATIONAL AERONAUTICS AND SPACE ADMINISTRATION (NASA).

THE REPORT FROM NASA IN THIS MATTER RELATES THAT THE SOLICITATION IN QUESTION WAS ISSUED ON MARCH 24, 1971, AND REQUESTED PROPOSALS FOR EIGHT TRIPLE REDUNDANT BINARY CODED DECIMAL TO BINARY CONVERTERS, SPARE PARTS AND DOCUMENTATION. THIRTEEN COMPANIES SUBMITTED PROPOSALS. SIX PROPOSALS WERE FOUND TO BE TECHNICALLY UNACCEPTABLE INITIALLY AND THE REMAINING SEVEN, INCLUDING YOUR PROPOSAL, REQUIRED ADDITIONAL TECHNICAL INFORMATION OR CLARIFICATION TO PERMIT FINAL TECHNICAL EVALUATION. SUCH DATA WAS REQUESTED BY LETTERS TO EACH OF THE SEVEN COMPANIES ON JULY 23, 1971.

THE LETTER TO YOUR COMPANY, IN PERTINENT PART, IS AS FOLLOWS:

"YOUR PROPOSAL SUBMITTED IN RESPONSE TO THE SUBJECT RFP LACKED SUFFICIENT DISCUSSION FOR COMPLETE TECHNICAL EVALUATION IN THE FOLLOWING AREAS:

A. SPECIFICATIONS CALL FOR THE USE OF FULL ADDER LOGIC APPROACH FOR THE BINARY CODE DECIMAL TO BINARY CONVERSION. PROVIDE DETAILED DISCUSSION AND DIAGRAM OF THE CONVERTOR."

YOUR RESPONSE TO THE ABOVE, AGAIN IN PERTINENT PART, IS SET FORTH IN YOUR LETTER OF AUGUST 3, 1971, AS FOLLOWS:

"1. DECIMAL TO BINARY CONVERSION.

THE MAJOR POINT OF CONCERN HERE IS THAT FULL ADDER LOGIC SHOULD BE EMPLOYED. A FULL ADDER IS A COMBINATION OF LOGIC ELEMENTS WHICH PROVIDES A CARRY OUTPUT IN ADDITION TO THE SUM OUTPUT. BY THE ADDITION OF A VERY MINIMAL AMOUNT OF LOGIC, AND BY REDEFINING SOME OF THE SIGNALS, A FULL ADDER CAN BECOME A FULL SUBTRACTOR. FREQUENTLY NOWADAYS THE TERM 'FULL ADDER' IS SUFFICIENTLY COMPREHENSIVE IN ITS MEANING TO INCLUDE BOTH ADDITION AND SUBTRACTION. OUR PROPOSAL DESCRIBES TWO STEPS IN THE DECIMAL TO BINARY CONVERSION CYCLE, AND BOTH STEPS INCLUDE FULL ADDERS. THE OUTPUTS FROM THE FIRST STEP PROVIDE INPUT SIGNALS FOR THE SECOND STEP.

THE SECOND STEP IN THE D TO B CONVERSION IS ACCOMPLISHED IN SERIAL CONFIGURATION BY A SHIFT REGISTER AND WHAT ARE TERMED 'SERIAL SUBTRACTORS' (PARAGRAPHS 2.4, 2.4.1, 2.4.2 AND 2.4.3, AND FIGURE 2-4). THESE SUBTRACTORS ARE ENTIRELY CONVENTIONAL FULL ADDERS WITH DIFFERENCE AND BORROW OUTPUTS, FOR USE IN SERIAL CALCULATION. THE EMPLOYMENT OF FOUR SUBTRACTORS WITHIN ONE CALCULATING LOOP, RATHER THAN ONLY ONE, IS SOMEWHAT UNCONVENTIONAL, BUT THE SUBTRACTORS THEMSELVES ARE COMMON FULL ADDERS."

THE CONTRACTING OFFICER'S REPLY OF OCTOBER 5, 1971, TO YOUR FIRM, MADE THE FOLLOWING STATEMENTS:

"YOUR PROPOSAL IS CONSIDERED TECHNICALLY UNACCEPTABLE AND NOT RESPONSIVE TO THE REQUIREMENTS SET FORTH IN THE SUBJECT RFP. THE PROPOSAL DID NOT DESCRIBE A METHOD OF CONVERSION UTILIZING THE CONVENTIONAL FULL ADDER. YOUR APPROACH TO THIS MAJOR TECHNICAL REQUIREMENT DOES NOT COMPLY WITH PARAGRAPH 3.3.1 OF GSFC SPECIFICATION S-573-313. THEREFORE, YOUR PROPOSAL IS NOT ACCEPTABLE FOR THIS PROCUREMENT, AND A REVISION THERETO WILL NOT BE CONSIDERED."

YOUR SUBSEQUENT PROTEST TO OUR OFFICE AGAINST REJECTION OF YOUR PROPOSAL CONTENDS THAT YOUR PROPOSAL WAS RESPONSIVE TO THE RFP AND THE CLARIFICATION REQUEST, AND THAT THE BASIS FOR REJECTION WAS INVALID SINCE THE SOLICITATION DID NOT REQUIRE DESCRIPTION OF A METHOD OF CONVERSION UTILIZING THE CONVENTIONAL FULL ADDER. YOU ASSERT THAT THIS IS A NEW REQUIREMENT ADDED BY THE CONTRACTING OFFICER'S LETTER OF OCTOBER 5, 1971.

THE STATEMENT OF THE CONTRACTING OFFICER IN RESPONSE TO YOUR PROTEST CONTAINS THE FOLLOWING:

"3. DISCUSSION OF THE SPECIFICATIONS

THE RFP SPECIFICATION S-573-P-13 DATED NOVEMBER 16, 1970 SUBPARAGRAPH 3.3.1 STATES:

'EACH BCD CONVERTER WILL USE FULL ADDER LOGIC AND THE CONVERSION CYCLE WILL NOT EXCEED FIVE (5) MICRO SECONDS.'

THE PURPOSE OF THE BCD/BC UNIT IS TO PROVIDE PARALLEL BINARY TIME INFORMATION TO THE OPERATION OF STATION COMMAND EQUIPMENT (SCE) AND STATION DATA ACQUISITION AND CONTROL EQUIPMENT (STADAC) USED IN THE NASA NETWORK TRACKING SYSTEMS. ALL OF THE COMPUTERS IN BOTH THE SCE AND STADAC ARE PROGRAMMED TO ACCEPT THIS FORM OF TIME INFORMATION. THE FULL ADDER LOGIC TECHNIQUE THROUGHOUT FOR THE BCD/BC IS CONSIDERED AS THE SIMPLEST APPROACH IN OBTAINING THE REQUIRED DATA. THE SEMI CONDUCTOR INDUSTRY HAS DEVELOPED BINARY FULL ADDER LOGIC CHIPS WHICH ENHANCE SIMPLICITY OF THESE UNITS AND EASE OF FIELD MAINTENANCE BY SIMPLE RIPPLE ADDITION. THESE WERE THE PRIMARY REASONS FOR OUR SELECTION OF AND THE REQUIREMENT FOR THE USE OF THE FULL ADDER LOGIC TECHNIQUE THROUGHOUT RATHER THAN THE HIGH SPEED SERIAL SHIFTING (ADDITION OR SUBTRACTION) TECHNIQUE.

WHILE OTHER TECHNIQUES COULD HAVE BEEN SPECIFIED AND COULD RESULT IN BCD/BC CONVERTERS, SUCH CONVERTERS WOULD HAVE INTERENT INFERIOR CHARACTERISTICS. FOR THIS REASON THE USE OF FULL ADDER LOGIC WAS SPECIFIED AND CANNOT REASONABLY BE CONSIDERED OPEN TO DEVIATION OR SUBSTITUTION. FULL ADDER LOGIC USED THROUGHOUT THE SYSTEM WAS ONE OF THE SIGNIFICANT CRITERIA UPON WHICH PROPOSALS WERE EVALUATED FOR TECHNICAL ACCEPTABILITY. IT IS NOTEWORTHY TO STATE THAT OF THE THIRTEEN COMPANIES SUBMITTING DETAILED TECHNICAL PROPOSALS, ONLY DDI FAILED TO UTILIZE THE FULL ADDER LOGIC AND CLARITY OF THE RFP IN THE USE OF FULL ADDER LOGIC IS THEREFORE AMPLY DEMONSTRATED AND IT CANNOT REASONABLY BE MISINTERPRETED AS STATED BY DDI AS BOTH 'CONVENTIONAL' AND 'UNCONVENTIONAL'.

"4. DISCUSSION OF DDI PROPOSAL

THE INITIAL EVALUATION BY THE COGNIZANT TECHNICAL EVALUATION TEAM CONCLUDED THAT THE DDI PROPOSAL WAS TECHNICALLY UNACCEPTABLE FOR REASONS INCLUDING ITS PROPOSED USE OF FULL ADDER LOGIC TECHNIQUE IN ONLY APPROXIMATELY HALF OF THE CONVERTER WITH THE USE OF A RATHER COMPLEX HYBRID SYSTEM FOR THE REMAINDER. SINCE THE DDI PROPOSAL APPEARED TO BE IN THE COMPETITIVE RANGE ON THE ASSUMPTION THAT USE OF THE HIGH SPEED SERIAL SHIFTING TECHNIQUE WAS AN OVERSIGHT, IT WAS CONSIDERED APPROPRIATE TO RETAIN THEM AS A POTENTIAL SOURCE ALONG WITH THE SIX OTHER OFFERORS, EACH TO SUPPLY ADDITIONAL TECHNICAL INFORMATION AND CLARIFICATIONS PERMITTING FULL AND COMPLETE EVALUATION OF THEIR PROPOSED CONVERTER UNITS.

IN ITS RESPONSE, DATED AUGUST 3, 1971 SUFFICIENT DETAIL CONCERNING THE BIT ERROR DETECTION WAS SUPPLIED. HOWEVER, THE COMPANY MERELY ELABORATED ON ITS USE OF THE FULL ADDER LOGIC IN PART OF THE CONVERTER AND DEFENDED ITS USE OF THE HIGH SPEED SERIAL SHIFTING IN THE BALANCE OF THE UNIT. THIS WAS INTERPRETED AS RECOGNITION BY THE COMPANY THAT FULL ADDER LOGIC THROUGHOUT THE ENTIRE CONVERTER WAS REQUIRED BY THE SPECIFICATIONS BUT THAT DDI PREFERRED TO SUPPLY A UNIT UTILIZING BOTH FULL ADDER LOGIC AND HIGH SPEED SERIAL SHIFTING TECHNIQUES. THE REASON CITED BY DDI IN PROPOSING EQUIPMENT AS THEY DID WAS THAT IT WOULD BE MORE ECONOMICAL. CONSEQUENTLY, DDI WAS PROPOSING TO FURNISH CONVERTERS NOT MEETING GSFC SPECIFICATIONS AND INTENDED FIELD USAGE TO GAIN A PRICE ADVANTAGE. APPEARS AS THOUGH DDI WAS HOPEFUL THAT WE WOULD ACCEPT THEIR INTERPRETATION PERMITTING A CIRCUMVENTION OF THE SPECIFICATION AS A PRICE TRADE OFF."

IN VIEW OF THE FOREGOING, THE BASIC QUESTIONS TO BE RESOLVED ARE WHAT THE SPECIFICATIONS REQUIRED IN STATING THAT "EACH BCD CONVERTER WILL USE FULL ADDER LOGIC", AND WHETHER YOUR PROPOSAL CONFORMED TO THOSE REQUIREMENTS. AS INDICATED ABOVE, THE CONTRACTING OFFICER TAKES THE POSITION THAT FULL ADDER LOGIC MEANS FULL ADDER, AND NO SUBTRACTOR. AS EVIDENCE OF THE CORRECTNESS OF THIS POSITION, THE CONTRACTING OFFICER SUBMITS THE FACT THAT TWELVE OF THE THIRTEEN COMPANIES WHO RESPONDED INTERPRETED THE SPECIFICATIONS THE SAME WAY AND PROPOSED ONLY FULL ADDER LOGIC, WHILE YOUR COMPANY WAS THE ONLY ONE TO PROPOSE USE OF SERIAL SUBTRACTORS IN THE SECOND STAGE OF THE CONVERTER.

ON THE OTHER HAND, YOUR CONTENTION THAT YOUR PROPOSAL WAS RESPONSIVE TO THE SOLICITATION AND THE CLARIFICATION REQUEST IS BASED ON YOUR ALLEGATION THAT THE TERM "FULL ADDER" IS SUFFICIENTLY COMPREHENSIVE TO INCLUDE BOTH ADDITION AND SUBTRACTION. DESPITE THIS ALLEGATION, HOWEVER, YOUR STATEMENT THAT A FULL ADDER CAN BECOME A FULL SUBTRACTOR BY THE ADDITION OF A VERY MINIMAL AMOUNT OF LOGIC AND BY REDEFINING SOME OF THE SIGNALS, WOULD APPEAR TO INDICATE THAT A FULL SUBTRACTOR IS SOMETHING MORE THAN A FULL ADDER. MOREOVER, YOUR CHARACTERIZATION OF YOUR USE OF SERIAL SUBTRACTORS IN THE SECOND STAGE OF THE CONVERTER AS SOMEWHAT UNCONVENTIONAL WOULD LIKEWISE APPEAR TO INDICATE AN ACKNOWLEDGEMENT ON YOUR PART THAT YOUR PROPOSAL DID NOT FALL WITHIN THE CONVENTIONAL DEFINITION OF FULL ADDER LOGIC.

SOME CONVENTIONAL DEFINITIONS MAY BE FOUND IN THE AMERICAN NATIONAL STANDARD VOCABULARY FOR INFORMATION PROCESSING, APPROVED FEBRUARY 18, 1970, BY THE AMERICAN NATIONAL STANDARDS INSTITUTE, INC., WHICH CONTAINS THE FOLLOWING:

"ADDER (1) A DEVICE WHOSE OUTPUT IS A REPRESENTATION OF THE SUM OF THE QUANTITIES REPRESENTED BY ITS INPUTS

(2) SEE HALF-ADDER

ADDER-SUBTRACTOR, A DEVICE WHOSE OUTPUT IS A REPRESENTATION OF EITHER THE ARITHMETIC SUM OR DIFFERENCE, OR BOTH, OF THE QUANTITIES REPRESENTED BY ITS INPUTS.

HALF-ADDER

A COMBINATIONAL LOGIC ELEMENT HAVING TWO OUTPUTS, S AND C, AND TWO INPUTS, A AND B, SUCH THAT THE OUTPUTS ARE RELATED TO THE INPUTS ACCORDING TO THE FOLLOWING TABLE.

INPUT OUTPUT

A B C S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

S DENOTES 'SUM WITHOUT CARRY,' C DENOTES 'CARRY.' TWO HALF-ADDERS MAY BE USED FOR PERFORMING BINARY ADDITION."

THE AUTOMATIC DATA PROCESSING GLOSSARY, PROVIDED BY THE BUREAU OF THE BUDGET FOR USE AS AN AUTHORITATIVE REFERENCE BY ALL OFFICIALS AND EMPLOYEES OF THE EXECUTIVE BRANCH OF THE GOVERNMENT, DEFINES AN ADDER AS A DEVICE WHICH FORMS, AS OUTPUT, THE SUM OF TWO OR MORE NUMBERS PRESENTED AS INPUT. A HALF-ADDER IS DEFINED AS A CIRCUIT HAVING TWO OUTPUT POINTS REPRESENTING SUM AND CARRY AND TWO INPUT POINTS REPRESENTING ADDEND AND AUGEND. TWO HALF-ADDERS, PROPERLY CONNECTED, MAY BE USED FOR PERFORMING BINARY ADDITION AND FORM A FULL SERIAL ADDER.

SINCE THE ABOVE DEFINITIONS OF ADDER AND HALF-ADDER DO NOT INCLUDE SUBTRACTION, AND SINCE A SEPARATE DEFINITION IS PROVIDED FOR ADDER SUBTRACTOR, WE FIND NO SUPPORT FOR YOUR ALLEGATION THAT THE TERM FULL ADDER IS BROAD ENOUGH TO INCLUDE BOTH ADDITION AND SUBTRACTION. THE FACT THAT NONE OF THE OTHER TWELVE OFFERORS INTERPRETED THE SPECIFICATIONS AS ALLOWING USE OF SUBTRACTION TENDS TO SUBSTANTIATE THE POSITION OF THE CONTRACTING OFFICER, RATHER THAN YOUR POSITION, ON THE INTERPRETATION OF THE SPECIFICATIONS.

PARAGRAPH 3-805.1(A) OF THE NASA PROCUREMENT REGULATION PROVIDES THAT DISCUSSIONS SHALL BE HELD WITH ALL RESPONSIBLE OFFERORS WHO SUBMIT PROPOSALS WITHIN A COMPETITIVE RANGE, PRICE AND OTHER FACTORS CONSIDERED. THIS OFFICE HAS HELD THAT "OTHER FACTORS" INCLUDES THE TECHNICAL ACCEPTABILITY OF PROPOSALS. B-170317, FEBRUARY 2, 1971.

IN THE PRESENT CASE, YOUR COMPANY WAS INCLUDED IN THE FIRST ROUND OF DISCUSSIONS AFTER THE INITIAL EVALUATION. HOWEVER, WHEN YOUR RESPONSE MADE NO CHANGE IN THE CONFIGURATION OF THE SECOND STAGE OF THE CONVERTER, BUT MERELY DEFENDED YOUR ORIGINAL SYSTEM BY ATTEMPTING TO BROADEN THE DEFINITION OF FULL ADDER TO INCLUDE BOTH ADDITION AND SUBTRACTION, IT BECAME APPARENT THAT YOUR PROPOSAL DID NOT CONFORM TO THE SPECIFICATIONS. WE THEREFORE SEE NO JUSTIFIABLE BASIS FOR DISAGREEING WITH THE DETERMINATION THAT YOUR PROPOSAL WAS TECHNICALLY UNACCEPTABLE AND NOT RESPONSIVE TO THE REQUIREMENTS OF THE RFP, AND WE ARE UNABLE TO CONCLUDE THAT FURTHER DISCUSSIONS WITH YOUR FIRM WERE REQUIRED. SEE 49 COMP. GEN. 309 (1969).

CONCERNING YOUR CONTENTION THAT THE SPECIFICATIONS DID NOT REQUIRE USE OF A "CONVENTIONAL" FULL ADDER AND THAT SUCH REQUIREMENT WAS ADDED BY THE CONTRACTING OFFICER'S LETTER NOTIFYING YOU THAT YOUR PROPOSAL WAS TECHNICALLY UNACCEPTABLE, WE BELIEVE THE RECORD ESTABLISHES THAT EVALUATION OF YOUR PROPOSAL WAS IN ACCORDANCE WITH THE SPECIFICATIONS. ANY EVENT, THE NOTICE WAS NOT INTENDED AS A COMPLETE AND COMPREHENSIVE STATEMENT OF THE REASONS FOR REJECTION OF YOUR PROPOSAL. NASA PROCUREMENT REGULATION DIRECTIVE 70-15, DATED DECEMBER 1, 1970, PROVIDES IN PARAGRAPH III.D.(3E THAT:

"CONCERNS WHOSE PROPOSALS ARE NO LONGER TO BE CONSIDERED FOR CONTRACT AWARD WILL BE PROMPTLY SO NOTIFIED, TOGETHER WITH A GENERAL, REASONABLY BRIEF EXPLANATION OF THE REASONS. IF ANY CONCERN SO REQUESTS IN WRITING, IT WILL BE ACCORDED A FORMAL DEBRIEFING *** ."

IT WOULD APPEAR THAT THE BRIEF, GENERAL EXPLANATION OF THE REASONS FOR REJECTION OF YOUR PROPOSAL MERELY EMPLOYED TERMINOLOGY YOU HAD CHOSEN TO DESCRIBE YOUR PROPOSAL, SINCE THE WORD "UNCONVENTIONAL" WAS FIRST INTRODUCED INTO THE RECORD IN YOUR LETTER OF EXPLANATION. UNDER THE ABOVE DIRECTIVE, IT WAS INCUMBENT ON YOUR FIRM TO REQUEST, IN WRITING, A DEBRIEFING IF YOU DESIRED A FULL EXPLANATION OF THE REASONS FOR THE TECHNICAL UNACCEPTABILITY OF YOUR PROPOSAL. FOR THE REASONS STATED, WE FIND NO BASIS FOR LEGAL OBJECTION TO THE ACTIONS OF NASA IN EVALUATING AND REJECTING YOUR PROPOSAL. ACCORDINGLY, YOUR PROTEST IS DENIED.